<?xml version="1.0" encoding="UTF-8" ?><!-- generator=Zoho Sites --><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><atom:link href="https://www.learnchipdesign.com/blogs/systemverilog/feed" rel="self" type="application/rss+xml"/><title>Learn Chip Design - Blog , Systemverilog</title><description>Learn Chip Design - Blog , Systemverilog</description><link>https://www.learnchipdesign.com/blogs/systemverilog</link><lastBuildDate>Fri, 07 Nov 2025 06:59:01 +0530</lastBuildDate><generator>http://zoho.com/sites/</generator><item><title><![CDATA[DVCON 2024]]></title><link>https://www.learnchipdesign.com/blogs/post/Serial-bus-debugger</link><description><![CDATA[Abstract- Serial bus analyzer presented here is generic serial bus debugger which can basically monitor single input line for any serial bus protocol ]]></description><content:encoded><![CDATA[<p><span style="color:inherit;"><img src="/Tue%20Sep%2017%202024.png" alt=""/></span><br/></p><div><div><div><div style="text-align:center;"><span style="font-weight:400;font-size:24px;">Abstract- Serial bus analyzer presented here is generic serial bus debugger which can basically monitor single input line for any serial bus protocol and displays the frames/state and values both big and little endian in a hex format on the waveform like gtkwaves, VCS etc. The design is protocol agn...</span></div></div></div></div></br/></img>]]></content:encoded><pubDate>Tue, 17 Sep 2024 00:55:37 +0530</pubDate></item><item><title><![CDATA[Welcome to world of ASIC Verification ]]></title><link>https://www.learnchipdesign.com/blogs/post/welcome-to-world-of-asic-verification</link><description><![CDATA[A Brief introduction to ASIC Verification]]></description><content:encoded><![CDATA[A Brief introduction to ASIC Verification]]></content:encoded><pubDate>Sat, 11 May 2024 09:54:53 +0530</pubDate></item></channel></rss>