Blog tagged as SystemVerilog

UVM macros to make life easier

10.09.24 11:26 PM By Advane Harshal - Comment(s)

While creating any new component or object in UVM we first register it with the factory,

We usually use the macros


 // Code 

`uvm_object_utils(my_sequence)   
function new(string name="my_sequence");     
super.new(name);   
endfunction

Most of the time I write nothi...

Welcome to world of ASIC Verification 

11.05.24 09:54 AM By Advane Harshal - Comment(s)
A Brief introduction to ASIC Verification